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| author |  OszkarSemerath <oszka@152.66.252.189> | 2017-10-13 13:36:23 +0200 |
|---|---|---|
| committer | OszkarSemerath <oszka@152.66.252.189> | 2017-10-13 13:36:23 +0200 |
| commit | 41938f5b15d0dc4196f4842d85e5cbf6b4b161f1 (patch) | |
| tree | adcdea591733f13b629224904847a4d98314db6f /Solvers | |
| parent | :lipstick: (diff) | |
| download | VIATRA-Generator-41938f5b15d0dc4196f4842d85e5cbf6b4b161f1.tar.gz VIATRA-Generator-41938f5b15d0dc4196f4842d85e5cbf6b4b161f1.tar.zst VIATRA-Generator-41938f5b15d0dc4196f4842d85e5cbf6b4b161f1.zip | |
By default, Alloy uses filtered type ORM mapping
Diffstat (limited to 'Solvers')
| -rw-r--r-- | Solvers/Alloy-Solver/hu.bme.mit.inf.dlsreasoner.alloy.reasoner/src/hu/bme/mit/inf/dlsreasoner/alloy/reasoner/AlloySolver.xtend | 6 |
1 files changed, 3 insertions, 3 deletions
diff --git a/Solvers/Alloy-Solver/hu.bme.mit.inf.dlsreasoner.alloy.reasoner/src/hu/bme/mit/inf/dlsreasoner/alloy/reasoner/AlloySolver.xtend b/Solvers/Alloy-Solver/hu.bme.mit.inf.dlsreasoner.alloy.reasoner/src/hu/bme/mit/inf/dlsreasoner/alloy/reasoner/AlloySolver.xtend index b9723d18..f5a9510d 100644 --- a/Solvers/Alloy-Solver/hu.bme.mit.inf.dlsreasoner.alloy.reasoner/src/hu/bme/mit/inf/dlsreasoner/alloy/reasoner/AlloySolver.xtend +++ b/Solvers/Alloy-Solver/hu.bme.mit.inf.dlsreasoner.alloy.reasoner/src/hu/bme/mit/inf/dlsreasoner/alloy/reasoner/AlloySolver.xtend | |||
| @@ -7,7 +7,7 @@ import hu.bme.mit.inf.dlsreasoner.alloy.reasoner.builder.AlloyModelInterpretatio | |||
| 7 | import hu.bme.mit.inf.dlsreasoner.alloy.reasoner.builder.AlloyModelInterpretation_TypeInterpretation_FilteredTypes | 7 | import hu.bme.mit.inf.dlsreasoner.alloy.reasoner.builder.AlloyModelInterpretation_TypeInterpretation_FilteredTypes |
| 8 | import hu.bme.mit.inf.dlsreasoner.alloy.reasoner.builder.Logic2AlloyLanguageMapper | 8 | import hu.bme.mit.inf.dlsreasoner.alloy.reasoner.builder.Logic2AlloyLanguageMapper |
| 9 | import hu.bme.mit.inf.dlsreasoner.alloy.reasoner.builder.Logic2AlloyLanguageMapperTrace | 9 | import hu.bme.mit.inf.dlsreasoner.alloy.reasoner.builder.Logic2AlloyLanguageMapperTrace |
| 10 | import hu.bme.mit.inf.dlsreasoner.alloy.reasoner.builder.Logic2AlloyLanguageMapper_TypeMapper_InheritanceAndHorizontal | 10 | import hu.bme.mit.inf.dlsreasoner.alloy.reasoner.builder.Logic2AlloyLanguageMapper_TypeMapper_FilteredTypes |
| 11 | import hu.bme.mit.inf.dslreasoner.AlloyLanguageStandaloneSetupGenerated | 11 | import hu.bme.mit.inf.dslreasoner.AlloyLanguageStandaloneSetupGenerated |
| 12 | import hu.bme.mit.inf.dslreasoner.alloyLanguage.AlloyLanguagePackage | 12 | import hu.bme.mit.inf.dslreasoner.alloyLanguage.AlloyLanguagePackage |
| 13 | import hu.bme.mit.inf.dslreasoner.logic.model.builder.LogicReasoner | 13 | import hu.bme.mit.inf.dslreasoner.logic.model.builder.LogicReasoner |
| @@ -25,7 +25,7 @@ class AlloySolver extends LogicReasoner{ | |||
| 25 | x.createInjectorAndDoEMFRegistration | 25 | x.createInjectorAndDoEMFRegistration |
| 26 | } | 26 | } |
| 27 | 27 | ||
| 28 | val Logic2AlloyLanguageMapper forwardMapper = new Logic2AlloyLanguageMapper(new Logic2AlloyLanguageMapper_TypeMapper_InheritanceAndHorizontal) | 28 | val Logic2AlloyLanguageMapper forwardMapper = new Logic2AlloyLanguageMapper(new Logic2AlloyLanguageMapper_TypeMapper_FilteredTypes) |
| 29 | val AlloyHandler handler = new AlloyHandler | 29 | val AlloyHandler handler = new AlloyHandler |
| 30 | val Alloy2LogicMapper backwardMapper = new Alloy2LogicMapper | 30 | val Alloy2LogicMapper backwardMapper = new Alloy2LogicMapper |
| 31 | 31 | ||
| @@ -77,7 +77,7 @@ class AlloySolver extends LogicReasoner{ | |||
| 77 | //val res = answers.map | 77 | //val res = answers.map |
| 78 | sols.map[ | 78 | sols.map[ |
| 79 | new AlloyModelInterpretation( | 79 | new AlloyModelInterpretation( |
| 80 | new AlloyModelInterpretation_TypeInterpretation_FilteredTypes, | 80 | forwardMapper.typeMapper.typeInterpreter, |
| 81 | it as A4Solution, | 81 | it as A4Solution, |
| 82 | forwardMapper, | 82 | forwardMapper, |
| 83 | modelResult.trace as Logic2AlloyLanguageMapperTrace | 83 | modelResult.trace as Logic2AlloyLanguageMapperTrace |