1 files changed, 1 insertions, 1 deletions

diff --git a/Solvers/Alloy-Solver/hu.bme.mit.inf.dlsreasoner.alloy.reasoner/src/hu/bme/mit/inf/dlsreasoner/alloy/reasoner/builder/AlloyModelInterpretation.xtend b/Solvers/Alloy-Solver/hu.bme.mit.inf.dlsreasoner.alloy.reasoner/src/hu/bme/mit/inf/dlsreasoner/alloy/reasoner/builder/AlloyModelInterpretation.xtend
index 107aa001..29eabe2c 100644
--- a/Solvers/Alloy-Solver/hu.bme.mit.inf.dlsreasoner.alloy.reasoner/src/hu/bme/mit/inf/dlsreasoner/alloy/reasoner/builder/AlloyModelInterpretation.xtend
+++ b/Solvers/Alloy-Solver/hu.bme.mit.inf.dlsreasoner.alloy.reasoner/src/hu/bme/mit/inf/dlsreasoner/alloy/reasoner/builder/AlloyModelInterpretation.xtend
@@ -117,7 +117,7 @@ class AlloyModelInterpretation implements LogicModelInterpretation{
                 for(atom: allAtoms) {

                         val typeName = getName(atom.type)

                         val atomName = atom.name

-                        println(atom.toString + "  < -  " + typeName)

+//                      println(atom.toString + "  < -  " + typeName)

                         if(typeName == forwardTrace.logicLanguage.name) {

                                 this.logicLanguage = atom

                         } else if(typeName == "Int" || typeName == "seq/Int") {