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author | 2020-04-15 01:12:59 +0200 | |
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committer | 2020-04-15 01:12:59 +0200 | |
commit | 24e99dcce1d8803dea979c4a75682b278dccd7cf (patch) | |
tree | 63b7dccd9ceb6938205aab0aa0e9aff26fe786fd /Solvers/Alloy-Solver/hu.bme.mit.inf.dlsreasoner.alloy.reasoner/src | |
parent | check constraint is a special eval (diff) | |
download | VIATRA-Generator-24e99dcce1d8803dea979c4a75682b278dccd7cf.tar.gz VIATRA-Generator-24e99dcce1d8803dea979c4a75682b278dccd7cf.tar.zst VIATRA-Generator-24e99dcce1d8803dea979c4a75682b278dccd7cf.zip |
Alloy type mapping fix
Diffstat (limited to 'Solvers/Alloy-Solver/hu.bme.mit.inf.dlsreasoner.alloy.reasoner/src')
3 files changed, 10 insertions, 5 deletions
diff --git a/Solvers/Alloy-Solver/hu.bme.mit.inf.dlsreasoner.alloy.reasoner/src/hu/bme/mit/inf/dlsreasoner/alloy/reasoner/AlloySolver.xtend b/Solvers/Alloy-Solver/hu.bme.mit.inf.dlsreasoner.alloy.reasoner/src/hu/bme/mit/inf/dlsreasoner/alloy/reasoner/AlloySolver.xtend index 432651af..f6b0b4a5 100644 --- a/Solvers/Alloy-Solver/hu.bme.mit.inf.dlsreasoner.alloy.reasoner/src/hu/bme/mit/inf/dlsreasoner/alloy/reasoner/AlloySolver.xtend +++ b/Solvers/Alloy-Solver/hu.bme.mit.inf.dlsreasoner.alloy.reasoner/src/hu/bme/mit/inf/dlsreasoner/alloy/reasoner/AlloySolver.xtend | |||
@@ -16,6 +16,9 @@ import hu.bme.mit.inf.dslreasoner.logic.model.builder.LogicSolverConfiguration | |||
16 | import hu.bme.mit.inf.dslreasoner.logic.model.logicproblem.LogicProblem | 16 | import hu.bme.mit.inf.dslreasoner.logic.model.logicproblem.LogicProblem |
17 | import hu.bme.mit.inf.dslreasoner.logic.model.logicresult.ModelResult | 17 | import hu.bme.mit.inf.dslreasoner.logic.model.logicresult.ModelResult |
18 | import hu.bme.mit.inf.dslreasoner.workspace.ReasonerWorkspace | 18 | import hu.bme.mit.inf.dslreasoner.workspace.ReasonerWorkspace |
19 | import hu.bme.mit.inf.dlsreasoner.alloy.reasoner.builder.Logic2AlloyLanguageMapper_TypeMapper_InheritanceAndHorizontal | ||
20 | import hu.bme.mit.inf.dlsreasoner.alloy.reasoner.builder.Logic2AlloyLanguageMapper_TypeMapper | ||
21 | import hu.bme.mit.inf.dlsreasoner.alloy.reasoner.builder.Logic2AlloyLanguageMapper_TypeMapperTrace_InheritanceAndHorizontal | ||
19 | 22 | ||
20 | class AlloySolver extends LogicReasoner{ | 23 | class AlloySolver extends LogicReasoner{ |
21 | 24 | ||
@@ -25,7 +28,9 @@ class AlloySolver extends LogicReasoner{ | |||
25 | x.createInjectorAndDoEMFRegistration | 28 | x.createInjectorAndDoEMFRegistration |
26 | } | 29 | } |
27 | 30 | ||
28 | val Logic2AlloyLanguageMapper forwardMapper = new Logic2AlloyLanguageMapper(new Logic2AlloyLanguageMapper_TypeMapper_FilteredTypes) | 31 | val Logic2AlloyLanguageMapper_TypeMapper typeMapper = new Logic2AlloyLanguageMapper_TypeMapper_InheritanceAndHorizontal//Logic2AlloyLanguageMapper_TypeMapper_FilteredTypes |
32 | |||
33 | val Logic2AlloyLanguageMapper forwardMapper = new Logic2AlloyLanguageMapper(typeMapper) | ||
29 | val AlloyHandler handler = new AlloyHandler | 34 | val AlloyHandler handler = new AlloyHandler |
30 | val Alloy2LogicMapper backwardMapper = new Alloy2LogicMapper | 35 | val Alloy2LogicMapper backwardMapper = new Alloy2LogicMapper |
31 | 36 | ||
diff --git a/Solvers/Alloy-Solver/hu.bme.mit.inf.dlsreasoner.alloy.reasoner/src/hu/bme/mit/inf/dlsreasoner/alloy/reasoner/builder/AlloyModelInterpretation.xtend b/Solvers/Alloy-Solver/hu.bme.mit.inf.dlsreasoner.alloy.reasoner/src/hu/bme/mit/inf/dlsreasoner/alloy/reasoner/builder/AlloyModelInterpretation.xtend index 107aa001..bbee35fc 100644 --- a/Solvers/Alloy-Solver/hu.bme.mit.inf.dlsreasoner.alloy.reasoner/src/hu/bme/mit/inf/dlsreasoner/alloy/reasoner/builder/AlloyModelInterpretation.xtend +++ b/Solvers/Alloy-Solver/hu.bme.mit.inf.dlsreasoner.alloy.reasoner/src/hu/bme/mit/inf/dlsreasoner/alloy/reasoner/builder/AlloyModelInterpretation.xtend | |||
@@ -117,7 +117,7 @@ class AlloyModelInterpretation implements LogicModelInterpretation{ | |||
117 | for(atom: allAtoms) { | 117 | for(atom: allAtoms) { |
118 | val typeName = getName(atom.type) | 118 | val typeName = getName(atom.type) |
119 | val atomName = atom.name | 119 | val atomName = atom.name |
120 | println(atom.toString + " < - " + typeName) | 120 | //println(atom.toString + " < - " + typeName) |
121 | if(typeName == forwardTrace.logicLanguage.name) { | 121 | if(typeName == forwardTrace.logicLanguage.name) { |
122 | this.logicLanguage = atom | 122 | this.logicLanguage = atom |
123 | } else if(typeName == "Int" || typeName == "seq/Int") { | 123 | } else if(typeName == "Int" || typeName == "seq/Int") { |
diff --git a/Solvers/Alloy-Solver/hu.bme.mit.inf.dlsreasoner.alloy.reasoner/src/hu/bme/mit/inf/dlsreasoner/alloy/reasoner/builder/Logic2AlloyLanguageMapper_TypeMapper_FilteredTypes.xtend b/Solvers/Alloy-Solver/hu.bme.mit.inf.dlsreasoner.alloy.reasoner/src/hu/bme/mit/inf/dlsreasoner/alloy/reasoner/builder/Logic2AlloyLanguageMapper_TypeMapper_FilteredTypes.xtend index 397fb84b..3379ba20 100644 --- a/Solvers/Alloy-Solver/hu.bme.mit.inf.dlsreasoner.alloy.reasoner/src/hu/bme/mit/inf/dlsreasoner/alloy/reasoner/builder/Logic2AlloyLanguageMapper_TypeMapper_FilteredTypes.xtend +++ b/Solvers/Alloy-Solver/hu.bme.mit.inf.dlsreasoner.alloy.reasoner/src/hu/bme/mit/inf/dlsreasoner/alloy/reasoner/builder/Logic2AlloyLanguageMapper_TypeMapper_FilteredTypes.xtend | |||
@@ -123,8 +123,8 @@ class Logic2AlloyLanguageMapper_TypeMapper_FilteredTypes implements Logic2AlloyL | |||
123 | // 7. Each type is in the intersection of the supertypes | 123 | // 7. Each type is in the intersection of the supertypes |
124 | for(type : types.filter[it.supertypes.size>=2]) { | 124 | for(type : types.filter[it.supertypes.size>=2]) { |
125 | trace.specification.factDeclarations += createALSFactDeclaration => [ | 125 | trace.specification.factDeclarations += createALSFactDeclaration => [ |
126 | it.name = support.toIDMultiple("abstract",type.name) | 126 | it.name = support.toIDMultiple("supertypeIsInIntersection",type.name) |
127 | it.term = createALSEquals => [ | 127 | it.term = createALSSubset => [ |
128 | it.leftOperand = createALSReference => [ it.referred = type.lookup(typeTrace.type2ALSType) ] | 128 | it.leftOperand = createALSReference => [ it.referred = type.lookup(typeTrace.type2ALSType) ] |
129 | it.rightOperand = support.unfoldIntersection(type.supertypes.map[e| | 129 | it.rightOperand = support.unfoldIntersection(type.supertypes.map[e| |
130 | createALSReference => [it.referred = e.lookup(typeTrace.type2ALSType)]]) | 130 | createALSReference => [it.referred = e.lookup(typeTrace.type2ALSType)]]) |
@@ -135,7 +135,7 @@ class Logic2AlloyLanguageMapper_TypeMapper_FilteredTypes implements Logic2AlloyL | |||
135 | // 8. Each abstract type is equal to the union of the subtypes | 135 | // 8. Each abstract type is equal to the union of the subtypes |
136 | for(type : types.filter[isIsAbstract]) { | 136 | for(type : types.filter[isIsAbstract]) { |
137 | trace.specification.factDeclarations += createALSFactDeclaration => [ | 137 | trace.specification.factDeclarations += createALSFactDeclaration => [ |
138 | it.name = support.toIDMultiple("abstract",type.name) | 138 | it.name = support.toIDMultiple("abstractIsUnion",type.name) |
139 | it.term = createALSEquals => [ | 139 | it.term = createALSEquals => [ |
140 | it.leftOperand = createALSReference => [ it.referred = type.lookup(typeTrace.type2ALSType) ] | 140 | it.leftOperand = createALSReference => [ it.referred = type.lookup(typeTrace.type2ALSType) ] |
141 | it.rightOperand = support.unfoldPlus(type.subtypes.map[e| | 141 | it.rightOperand = support.unfoldPlus(type.subtypes.map[e| |