aboutsummaryrefslogtreecommitdiffstats
path: root/Solvers/Alloy-Solver/hu.bme.mit.inf.dlsreasoner.alloy.reasoner/src/hu/bme/mit/inf/dlsreasoner/alloy
diff options
context:
space:
mode:
authorLibravatar ArenBabikian <aren.babikian@mail.mcgill.ca>2020-06-07 20:19:26 -0400
committerLibravatar ArenBabikian <aren.babikian@mail.mcgill.ca>2020-06-07 20:19:26 -0400
commitadddfa282a0fe78bfdc5ffb967996d89293aa45c (patch)
treeef9b3dbed5bd4fa850d890a67b4c7ee3c1648782 /Solvers/Alloy-Solver/hu.bme.mit.inf.dlsreasoner.alloy.reasoner/src/hu/bme/mit/inf/dlsreasoner/alloy
parentVAMPIRE: Rebase on Master (diff)
parentVAMPIRE: Rebase on Master (diff)
downloadVIATRA-Generator-adddfa282a0fe78bfdc5ffb967996d89293aa45c.tar.gz
VIATRA-Generator-adddfa282a0fe78bfdc5ffb967996d89293aa45c.tar.zst
VIATRA-Generator-adddfa282a0fe78bfdc5ffb967996d89293aa45c.zip
Merge branch 'Vampire-New' into Vampire-New
Conflicts: Application/hu.bme.mit.inf.dslreasoner.application.ide/xtend-gen/hu/bme/mit/inf/dslreasoner/application/ide/.ApplicationConfigurationIdeModule.xtendbin Application/hu.bme.mit.inf.dslreasoner.application.ide/xtend-gen/hu/bme/mit/inf/dslreasoner/application/ide/.ApplicationConfigurationIdeSetup.xtendbin Application/hu.bme.mit.inf.dslreasoner.application/xtend-gen/hu/bme/mit/inf/dslreasoner/application/validation/QueryAndMetamodelValidator.java Domains/Examples/ModelGenExampleFAM_plugin/model/FamMetamodel.ecore Domains/Examples/ModelGenExampleFAM_plugin/plugin.xml Domains/hu.bme.mit.inf.dslreasoner.domains.alloyexamples/META-INF/MANIFEST.MF Domains/hu.bme.mit.inf.dslreasoner.domains.alloyexamples/src-gen/hu/bme/mit/inf/dslreasoner/domains/alloyexamples/ContentInNotLive.java Domains/hu.bme.mit.inf.dslreasoner.domains.alloyexamples/src-gen/hu/bme/mit/inf/dslreasoner/domains/alloyexamples/DirectSupertype.java Domains/hu.bme.mit.inf.dslreasoner.domains.alloyexamples/src-gen/hu/bme/mit/inf/dslreasoner/domains/alloyexamples/Live.java Domains/hu.bme.mit.inf.dslreasoner.domains.alloyexamples/src-gen/hu/bme/mit/inf/dslreasoner/domains/alloyexamples/LoopInInheritence.java Domains/hu.bme.mit.inf.dslreasoner.domains.alloyexamples/src-gen/hu/bme/mit/inf/dslreasoner/domains/alloyexamples/NonSymmetricOpposite.java Domains/hu.bme.mit.inf.dslreasoner.domains.alloyexamples/src-gen/hu/bme/mit/inf/dslreasoner/domains/alloyexamples/Opposite.java Domains/hu.bme.mit.inf.dslreasoner.domains.alloyexamples/src-gen/hu/bme/mit/inf/dslreasoner/domains/alloyexamples/OppositeDifferentClass.java Domains/hu.bme.mit.inf.dslreasoner.domains.alloyexamples/src-gen/hu/bme/mit/inf/dslreasoner/domains/alloyexamples/PatternContent.java Domains/hu.bme.mit.inf.dslreasoner.domains.yakindu.sgraph/META-INF/MANIFEST.MF Domains/hu.bme.mit.inf.dslreasoner.domains.yakindu.sgraph/plugin.xml Framework/hu.bme.mit.inf.dslreasoner.logic.model/META-INF/MANIFEST.MF Solvers/Alloy-Solver/hu.bme.mit.inf.dlsreasoner.alloy.reasoner/src/hu/bme/mit/inf/dlsreasoner/alloy/reasoner/builder/Logic2AlloyLanguageMapper_TypeScopeMapping.xtend Solvers/VIATRA-Solver/hu.bme.mit.inf.dslreasoner.visualisation/META-INF/MANIFEST.MF Tests/ca.mcgill.ecse.dslreasoner.standalone.test/src/ca/mcgill/ecse/dslreasoner/standalone/test/yakindu/Entry.java Tests/ca.mcgill.ecse.dslreasoner.standalone.test/src/ca/mcgill/ecse/dslreasoner/standalone/test/yakindu/Synchronization.java Tests/ca.mcgill.ecse.dslreasoner.standalone.test/src/ca/mcgill/ecse/dslreasoner/standalone/test/yakindu/impl/EntryImpl.java Tests/ca.mcgill.ecse.dslreasoner.standalone.test/src/ca/mcgill/ecse/dslreasoner/standalone/test/yakindu/impl/SynchronizationImpl.java
Diffstat (limited to 'Solvers/Alloy-Solver/hu.bme.mit.inf.dlsreasoner.alloy.reasoner/src/hu/bme/mit/inf/dlsreasoner/alloy')
-rw-r--r--Solvers/Alloy-Solver/hu.bme.mit.inf.dlsreasoner.alloy.reasoner/src/hu/bme/mit/inf/dlsreasoner/alloy/reasoner/builder/Logic2AlloyLanguageMapper_TypeScopeMapping.xtend46
1 files changed, 0 insertions, 46 deletions
diff --git a/Solvers/Alloy-Solver/hu.bme.mit.inf.dlsreasoner.alloy.reasoner/src/hu/bme/mit/inf/dlsreasoner/alloy/reasoner/builder/Logic2AlloyLanguageMapper_TypeScopeMapping.xtend b/Solvers/Alloy-Solver/hu.bme.mit.inf.dlsreasoner.alloy.reasoner/src/hu/bme/mit/inf/dlsreasoner/alloy/reasoner/builder/Logic2AlloyLanguageMapper_TypeScopeMapping.xtend
index 378c9553..a270cb73 100644
--- a/Solvers/Alloy-Solver/hu.bme.mit.inf.dlsreasoner.alloy.reasoner/src/hu/bme/mit/inf/dlsreasoner/alloy/reasoner/builder/Logic2AlloyLanguageMapper_TypeScopeMapping.xtend
+++ b/Solvers/Alloy-Solver/hu.bme.mit.inf.dlsreasoner.alloy.reasoner/src/hu/bme/mit/inf/dlsreasoner/alloy/reasoner/builder/Logic2AlloyLanguageMapper_TypeScopeMapping.xtend
@@ -1,4 +1,3 @@
1<<<<<<< HEAD
2package hu.bme.mit.inf.dlsreasoner.alloy.reasoner.builder 1package hu.bme.mit.inf.dlsreasoner.alloy.reasoner.builder
3 2
4import hu.bme.mit.inf.dslreasoner.logic.model.logiclanguage.Type 3import hu.bme.mit.inf.dslreasoner.logic.model.logiclanguage.Type
@@ -42,49 +41,4 @@ class Logic2AlloyLanguageMapper_AsConstraint implements Logic2AlloyLanguageMappe
42 ] 41 ]
43 ] 42 ]
44 } 43 }
45=======
46package hu.bme.mit.inf.dlsreasoner.alloy.reasoner.builder
47
48import hu.bme.mit.inf.dslreasoner.logic.model.logiclanguage.Type
49import hu.bme.mit.inf.dslreasoner.alloyLanguage.ALSDocument
50import hu.bme.mit.inf.dslreasoner.alloyLanguage.AlloyLanguageFactory
51
52interface Logic2AlloyLanguageMapper_TypeScopeMapping {
53 def void addLowerMultiplicity(ALSDocument document, Type type, int lowerMultiplicty, Logic2AlloyLanguageMapper mapper, Logic2AlloyLanguageMapperTrace trace)
54 def void addUpperMultiplicity(ALSDocument document, Type type, int upperMultiplicty, Logic2AlloyLanguageMapper mapper, Logic2AlloyLanguageMapperTrace trace)
55}
56
57class Logic2AlloyLanguageMapper_AsConstraint implements Logic2AlloyLanguageMapper_TypeScopeMapping {
58 val extension AlloyLanguageFactory factory = AlloyLanguageFactory.eINSTANCE
59 val Logic2AlloyLanguageMapper_Support support = new Logic2AlloyLanguageMapper_Support;
60 val Logic2AlloyLanguageMapper_TypeMapper typeMapper
61
62 new(Logic2AlloyLanguageMapper_TypeMapper mapper) {
63 this.typeMapper = mapper
64 }
65
66 override addLowerMultiplicity(ALSDocument document, Type type, int lowerMultiplicty, Logic2AlloyLanguageMapper mapper, Logic2AlloyLanguageMapperTrace trace) {
67 document.factDeclarations += createALSFactDeclaration => [
68 it.name = support.toID(#["LowerMultiplicity",support.toID(type.name),lowerMultiplicty.toString])
69 it.term = createALSLeq => [
70 it.leftOperand = createALSCardinality => [
71 it.operand = support.unfoldPlus(typeMapper.transformTypeReference(type,mapper,trace).map[t|createALSReference => [it.referred = t]].toList)
72 ]
73 it.rightOperand = createALSNumberLiteral => [it.value = lowerMultiplicty]
74 ]
75 ]
76 }
77
78 override addUpperMultiplicity(ALSDocument document, Type type, int upperMultiplicty, Logic2AlloyLanguageMapper mapper, Logic2AlloyLanguageMapperTrace trace) {
79 document.factDeclarations += createALSFactDeclaration => [
80 it.name = support.toID(#["UpperMultiplicity",support.toID(type.name),upperMultiplicty.toString])
81 it.term = createALSMeq => [
82 it.leftOperand = createALSCardinality => [
83 it.operand = support.unfoldPlus(typeMapper.transformTypeReference(type,mapper,trace).map[t|createALSReference => [it.referred = t]].toList)
84 ]
85 it.rightOperand = createALSNumberLiteral => [it.value = upperMultiplicty]
86 ]
87 ]
88 }
89>>>>>>> 25a4b1b5... VAMPIRE: post-submission push
90} \ No newline at end of file 44} \ No newline at end of file