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| author |  Kristóf Marussy <kris7topher@gmail.com> | 2019-10-29 17:32:38 +0100 |
|---|---|---|
| committer | Kristóf Marussy <kris7topher@gmail.com> | 2019-10-29 17:32:38 +0100 |
| commit | b15b3d49ead78c9124a98ab982a4488e4d7bc3d4 (patch) | |
| tree | bdc39d57ddf0a31f6f8e87a9b5a6b4ec6136d44e /Solvers/Alloy-Solver/hu.bme.mit.inf.dlsreasoner.alloy.reasoner/src/hu/bme/mit/inf/dlsreasoner/alloy/reasoner/builder/AlloyModelInterpretation.xtend | |
| parent | Remove empty src directories from build path (diff) | |
| download | VIATRA-Generator-b15b3d49ead78c9124a98ab982a4488e4d7bc3d4.tar.gz VIATRA-Generator-b15b3d49ead78c9124a98ab982a4488e4d7bc3d4.tar.zst VIATRA-Generator-b15b3d49ead78c9124a98ab982a4488e4d7bc3d4.zip | |
Alloy cardinality fixes
Diffstat (limited to 'Solvers/Alloy-Solver/hu.bme.mit.inf.dlsreasoner.alloy.reasoner/src/hu/bme/mit/inf/dlsreasoner/alloy/reasoner/builder/AlloyModelInterpretation.xtend')
| -rw-r--r-- | Solvers/Alloy-Solver/hu.bme.mit.inf.dlsreasoner.alloy.reasoner/src/hu/bme/mit/inf/dlsreasoner/alloy/reasoner/builder/AlloyModelInterpretation.xtend | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/Solvers/Alloy-Solver/hu.bme.mit.inf.dlsreasoner.alloy.reasoner/src/hu/bme/mit/inf/dlsreasoner/alloy/reasoner/builder/AlloyModelInterpretation.xtend b/Solvers/Alloy-Solver/hu.bme.mit.inf.dlsreasoner.alloy.reasoner/src/hu/bme/mit/inf/dlsreasoner/alloy/reasoner/builder/AlloyModelInterpretation.xtend index 107aa001..29eabe2c 100644 --- a/Solvers/Alloy-Solver/hu.bme.mit.inf.dlsreasoner.alloy.reasoner/src/hu/bme/mit/inf/dlsreasoner/alloy/reasoner/builder/AlloyModelInterpretation.xtend +++ b/Solvers/Alloy-Solver/hu.bme.mit.inf.dlsreasoner.alloy.reasoner/src/hu/bme/mit/inf/dlsreasoner/alloy/reasoner/builder/AlloyModelInterpretation.xtend | |||
| @@ -117,7 +117,7 @@ class AlloyModelInterpretation implements LogicModelInterpretation{ | |||
| 117 | for(atom: allAtoms) { | 117 | for(atom: allAtoms) { |
| 118 | val typeName = getName(atom.type) | 118 | val typeName = getName(atom.type) |
| 119 | val atomName = atom.name | 119 | val atomName = atom.name |
| 120 | println(atom.toString + " < - " + typeName) | 120 | // println(atom.toString + " < - " + typeName) |
| 121 | if(typeName == forwardTrace.logicLanguage.name) { | 121 | if(typeName == forwardTrace.logicLanguage.name) { |
| 122 | this.logicLanguage = atom | 122 | this.logicLanguage = atom |
| 123 | } else if(typeName == "Int" || typeName == "seq/Int") { | 123 | } else if(typeName == "Int" || typeName == "seq/Int") { |