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author | 2020-04-15 01:12:59 +0200 | |
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committer | 2020-04-15 01:12:59 +0200 | |
commit | 24e99dcce1d8803dea979c4a75682b278dccd7cf (patch) | |
tree | 63b7dccd9ceb6938205aab0aa0e9aff26fe786fd /Solvers/Alloy-Solver/hu.bme.mit.inf.dlsreasoner.alloy.reasoner/src/hu/bme/mit/inf/dlsreasoner/alloy/reasoner/AlloySolver.xtend | |
parent | check constraint is a special eval (diff) | |
download | VIATRA-Generator-24e99dcce1d8803dea979c4a75682b278dccd7cf.tar.gz VIATRA-Generator-24e99dcce1d8803dea979c4a75682b278dccd7cf.tar.zst VIATRA-Generator-24e99dcce1d8803dea979c4a75682b278dccd7cf.zip |
Alloy type mapping fix
Diffstat (limited to 'Solvers/Alloy-Solver/hu.bme.mit.inf.dlsreasoner.alloy.reasoner/src/hu/bme/mit/inf/dlsreasoner/alloy/reasoner/AlloySolver.xtend')
-rw-r--r-- | Solvers/Alloy-Solver/hu.bme.mit.inf.dlsreasoner.alloy.reasoner/src/hu/bme/mit/inf/dlsreasoner/alloy/reasoner/AlloySolver.xtend | 7 |
1 files changed, 6 insertions, 1 deletions
diff --git a/Solvers/Alloy-Solver/hu.bme.mit.inf.dlsreasoner.alloy.reasoner/src/hu/bme/mit/inf/dlsreasoner/alloy/reasoner/AlloySolver.xtend b/Solvers/Alloy-Solver/hu.bme.mit.inf.dlsreasoner.alloy.reasoner/src/hu/bme/mit/inf/dlsreasoner/alloy/reasoner/AlloySolver.xtend index 432651af..f6b0b4a5 100644 --- a/Solvers/Alloy-Solver/hu.bme.mit.inf.dlsreasoner.alloy.reasoner/src/hu/bme/mit/inf/dlsreasoner/alloy/reasoner/AlloySolver.xtend +++ b/Solvers/Alloy-Solver/hu.bme.mit.inf.dlsreasoner.alloy.reasoner/src/hu/bme/mit/inf/dlsreasoner/alloy/reasoner/AlloySolver.xtend | |||
@@ -16,6 +16,9 @@ import hu.bme.mit.inf.dslreasoner.logic.model.builder.LogicSolverConfiguration | |||
16 | import hu.bme.mit.inf.dslreasoner.logic.model.logicproblem.LogicProblem | 16 | import hu.bme.mit.inf.dslreasoner.logic.model.logicproblem.LogicProblem |
17 | import hu.bme.mit.inf.dslreasoner.logic.model.logicresult.ModelResult | 17 | import hu.bme.mit.inf.dslreasoner.logic.model.logicresult.ModelResult |
18 | import hu.bme.mit.inf.dslreasoner.workspace.ReasonerWorkspace | 18 | import hu.bme.mit.inf.dslreasoner.workspace.ReasonerWorkspace |
19 | import hu.bme.mit.inf.dlsreasoner.alloy.reasoner.builder.Logic2AlloyLanguageMapper_TypeMapper_InheritanceAndHorizontal | ||
20 | import hu.bme.mit.inf.dlsreasoner.alloy.reasoner.builder.Logic2AlloyLanguageMapper_TypeMapper | ||
21 | import hu.bme.mit.inf.dlsreasoner.alloy.reasoner.builder.Logic2AlloyLanguageMapper_TypeMapperTrace_InheritanceAndHorizontal | ||
19 | 22 | ||
20 | class AlloySolver extends LogicReasoner{ | 23 | class AlloySolver extends LogicReasoner{ |
21 | 24 | ||
@@ -25,7 +28,9 @@ class AlloySolver extends LogicReasoner{ | |||
25 | x.createInjectorAndDoEMFRegistration | 28 | x.createInjectorAndDoEMFRegistration |
26 | } | 29 | } |
27 | 30 | ||
28 | val Logic2AlloyLanguageMapper forwardMapper = new Logic2AlloyLanguageMapper(new Logic2AlloyLanguageMapper_TypeMapper_FilteredTypes) | 31 | val Logic2AlloyLanguageMapper_TypeMapper typeMapper = new Logic2AlloyLanguageMapper_TypeMapper_InheritanceAndHorizontal//Logic2AlloyLanguageMapper_TypeMapper_FilteredTypes |
32 | |||
33 | val Logic2AlloyLanguageMapper forwardMapper = new Logic2AlloyLanguageMapper(typeMapper) | ||
29 | val AlloyHandler handler = new AlloyHandler | 34 | val AlloyHandler handler = new AlloyHandler |
30 | val Alloy2LogicMapper backwardMapper = new Alloy2LogicMapper | 35 | val Alloy2LogicMapper backwardMapper = new Alloy2LogicMapper |
31 | 36 | ||