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author | OszkarSemerath <oszka@152.66.252.189> | 2017-07-05 15:00:37 +0200 |
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committer | OszkarSemerath <oszka@152.66.252.189> | 2017-07-05 15:00:37 +0200 |
commit | 53cf6e18913a9f0c7717ff84eedd56941944367a (patch) | |
tree | 09534b4fb4c1b3cb6949a403b2c3f196a21d060b /Solvers/Alloy-Solver/hu.bme.mit.inf.dlsreasoner.alloy.reasoner/src/hu/bme/mit/inf/dlsreasoner/alloy/reasoner/AlloySolver.xtend | |
parent | Added a try-catch to detect if a query cannot be translated (because, (diff) | |
download | VIATRA-Generator-53cf6e18913a9f0c7717ff84eedd56941944367a.tar.gz VIATRA-Generator-53cf6e18913a9f0c7717ff84eedd56941944367a.tar.zst VIATRA-Generator-53cf6e18913a9f0c7717ff84eedd56941944367a.zip |
Adding multiple model generation support for the alloy solver.
Diffstat (limited to 'Solvers/Alloy-Solver/hu.bme.mit.inf.dlsreasoner.alloy.reasoner/src/hu/bme/mit/inf/dlsreasoner/alloy/reasoner/AlloySolver.xtend')
-rw-r--r-- | Solvers/Alloy-Solver/hu.bme.mit.inf.dlsreasoner.alloy.reasoner/src/hu/bme/mit/inf/dlsreasoner/alloy/reasoner/AlloySolver.xtend | 12 |
1 files changed, 7 insertions, 5 deletions
diff --git a/Solvers/Alloy-Solver/hu.bme.mit.inf.dlsreasoner.alloy.reasoner/src/hu/bme/mit/inf/dlsreasoner/alloy/reasoner/AlloySolver.xtend b/Solvers/Alloy-Solver/hu.bme.mit.inf.dlsreasoner.alloy.reasoner/src/hu/bme/mit/inf/dlsreasoner/alloy/reasoner/AlloySolver.xtend index d0c7d320..65539155 100644 --- a/Solvers/Alloy-Solver/hu.bme.mit.inf.dlsreasoner.alloy.reasoner/src/hu/bme/mit/inf/dlsreasoner/alloy/reasoner/AlloySolver.xtend +++ b/Solvers/Alloy-Solver/hu.bme.mit.inf.dlsreasoner.alloy.reasoner/src/hu/bme/mit/inf/dlsreasoner/alloy/reasoner/AlloySolver.xtend | |||
@@ -16,6 +16,8 @@ import hu.bme.mit.inf.dslreasoner.logic.model.builder.LogicSolverConfiguration | |||
16 | import hu.bme.mit.inf.dslreasoner.logic.model.logicproblem.LogicProblem | 16 | import hu.bme.mit.inf.dslreasoner.logic.model.logicproblem.LogicProblem |
17 | import hu.bme.mit.inf.dslreasoner.logic.model.logicresult.ModelResult | 17 | import hu.bme.mit.inf.dslreasoner.logic.model.logicresult.ModelResult |
18 | import hu.bme.mit.inf.dslreasoner.workspace.ReasonerWorkspace | 18 | import hu.bme.mit.inf.dslreasoner.workspace.ReasonerWorkspace |
19 | import edu.mit.csail.sdg.alloy4compiler.translator.A4Solution | ||
20 | import java.util.List | ||
19 | 21 | ||
20 | class AlloySolver extends LogicReasoner{ | 22 | class AlloySolver extends LogicReasoner{ |
21 | 23 | ||
@@ -72,16 +74,16 @@ class AlloySolver extends LogicReasoner{ | |||
72 | } | 74 | } |
73 | 75 | ||
74 | override getInterpretations(ModelResult modelResult) { | 76 | override getInterpretations(ModelResult modelResult) { |
75 | val answers = (modelResult.representation as MonitoredAlloySolution).aswers.map[key] | 77 | //val answers = (modelResult.representation as MonitoredAlloySolution).aswers.map[key] |
76 | val res = answers.map [ | 78 | val sols = modelResult.representation// as List<A4Solution> |
79 | //val res = answers.map | ||
80 | sols.map[ | ||
77 | new AlloyModelInterpretation( | 81 | new AlloyModelInterpretation( |
78 | new AlloyModelInterpretation_TypeInterpretation_FilteredTypes, | 82 | new AlloyModelInterpretation_TypeInterpretation_FilteredTypes, |
79 | it, | 83 | it as A4Solution, |
80 | forwardMapper, | 84 | forwardMapper, |
81 | modelResult.trace as Logic2AlloyLanguageMapperTrace | 85 | modelResult.trace as Logic2AlloyLanguageMapperTrace |
82 | ) | 86 | ) |
83 | ] | 87 | ] |
84 | |||
85 | return res | ||
86 | } | 88 | } |
87 | } \ No newline at end of file | 89 | } \ No newline at end of file |